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ICIP
2003
IEEE
14 years 10 months ago
Parallel-pipelined architecture for 2-D ICT VLSI implementation
The Integer Cosine Transform (ICT) has been shown to be an alternative to the DCT for image processing. This paper presents a parallel-pipelined architecture of an 8x8 ICT(10, 9, ...
Juan A. Michell, Gustavo A. Ruiz, Angel M. Buron
UML
2005
Springer
14 years 2 months ago
Code Generation from UML Models with Semantic Variation Points
UML semantic variation points provide intentional degrees of freedom for the interpretation of the metamodel semantics. The interest of semantic variation points is that UML now b...
Franck Chauvel, Jean-Marc Jézéquel
ISCAS
2006
IEEE
116views Hardware» more  ISCAS 2006»
14 years 2 months ago
An asynchronous delta-sigma converter implementation
— In this paper an architecture, signal reconstruction algorithm and first-ever implementation of an asynchronous delta-sigma converter are presented. The signal reconstruction ...
Dazhi Wei, Vaibhav Garg, John G. Harris
TVLSI
2010
13 years 3 months ago
Design and Implementation of a Sort-Free K-Best Sphere Decoder
:- This paper describes the design and VLSI architecture for a 4x4 breadth first K-Best MIMO decoder using a 64 QAM scheme. A novel sort free approach to path extension, as well as...
Sudip Mondal, Ahmed M. Eltawil, Chung-An Shen, Kha...
CCECE
2009
IEEE
14 years 3 months ago
An ultra compact block cipher for serialized architecture implementations
In this paper, we present a new block cipher, referred as PUFFIN2, that is designed to be used with applications requiring very low circuit area. PUFFIN2 is designed to be impleme...
Cheng Wang, Howard M. Heys