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» Architecture and synthesis for multi-cycle communication
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DATE
2010
IEEE
154views Hardware» more  DATE 2010»
13 years 8 months ago
Computing robustness of FlexRay schedules to uncertainties in design parameters
Abstract--In the current environment of rapidly changing invehicle requirements and ever-increasing functional content for automotive EE systems, there are several sources of uncer...
Arkadeb Ghosal, Haibo Zeng, Marco Di Natale, Yakov...
ATVA
2009
Springer
142views Hardware» more  ATVA 2009»
14 years 2 months ago
Synthesis of Fault-Tolerant Distributed Systems
Abstract. A distributed system is fault-tolerant if it continues to perform correctly even when a subset of the processes becomes faulty. Faulttolerance is highly desirable but oft...
Rayna Dimitrova, Bernd Finkbeiner
ISCAS
2008
IEEE
109views Hardware» more  ISCAS 2008»
14 years 2 months ago
A dual-core programmable decoder for LDPC convolutional codes
Abstract— We present the concepts and realization of a highly parallelized decoder architecture for LDPC convolutional codes and tailbiting LDPC convolutional codes. This archite...
Marcos B. S. Tavares, Emil Matús, Steffen K...
DATE
1999
IEEE
162views Hardware» more  DATE 1999»
13 years 12 months ago
MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
Robert P. Dick, Niraj K. Jha
DAC
1996
ACM
13 years 11 months ago
Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis
This paper presents the design of a Videophone CoderDecoder Motion Estimator using two High-Level Synthesis tools. Indeed, the combination of a Control Flow Dominated part (comple...
Elisabeth Berrebi, Polen Kission, Serge Vernalde, ...