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» Architecture and synthesis for multi-cycle communication
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ERSA
2007
177views Hardware» more  ERSA 2007»
13 years 9 months ago
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
Xiaofang Wang, Sotirios G. Ziavras, Jie Hu
DAC
2006
ACM
14 years 8 months ago
Synthesis of high-performance packet processing pipelines
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
Cristian Soviani, Ilija Hadzic, Stephen A. Edwards
CORR
2006
Springer
112views Education» more  CORR 2006»
13 years 7 months ago
High-level synthesis under I/O Timing and Memory constraints
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
Philippe Coussy, Gwenolé Corre, Pierre Bome...
DSD
2002
IEEE
88views Hardware» more  DSD 2002»
14 years 18 days ago
The Synthesis of a Hardware Scheduler for Non-Manifest Loops
This paper1 addresses the hardware implementation of a dynamic scheduler for non-manifest data dependent periodic loops. Static scheduling techniques which are known to give near ...
Omar Mansour, Egbert Molenkamp, Thijs Krol
DAC
1999
ACM
13 years 12 months ago
ipChinook: an Integrated IP-based Design Framework for Distributed Embedded Systems
IPCHINOOK is a design tool for distributed embedded systems. It gains leverage from the use of a carefully chosen set of design ions that raise the level of designer interaction d...
Pai H. Chou, Ross B. Ortega, Ken Hines, Kurt Partr...