114 search results - page 18 / 23 » Architecture and synthesis for multi-cycle communication |
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To s...
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
Networks-on-Chip (NoCs) have been recently proposed as a promising solution to complex on-chip communication problems. The lack of an unified representation of applications and ar...
CNSR
2005
IEEE
14 years 1 months ago
2005
IEEE
A framework has been developed as a basis for design and implementation of adaptive Web systems. This framework and the respective architecture support the idea of high-level synt...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
We present practical algorithms for the synthesis of crosstalk cancelling equalizing filters. We examine designs optimized for the traditional l2 metric and introduce an approach ...