125 search results - page 13 / 25 » Area and delay trade-offs in the circuit and architecture de... |
FPL
2005
Springer
14 years 27 days ago
2005
Springer
Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate ...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
In this paper, we propose a new sensitivity based, statistical gate sizing method. Since circuit optimization effects the entire shape of the circuit delay distribution, it is dif...
CSREAESA
2004
13 years 8 months ago
2004
Adders are some of the most critical data path circuits requiring considerable design effort in order to "squeeze" out as much performance gain as possible. Many adder d...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
1 FPGAs are an appealing solution for the space-based remote sensing applications. However, in a low-earth orbit, configuration bits of SRAM-based FPGAs are susceptible to single-e...