125 search results - page 4 / 25 » Area and delay trade-offs in the circuit and architecture de... |
FPGA
2001
ACM
13 years 12 months ago
2001
ACM
The routing architecture of an FPGA consists of the length of the wires, the type of switch used to connect wires (buffered, unbuffered, fast or slow) and the topology of the inte...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Three-dimensional integrated circuits (3DICs) have the potential to reduce interconnect lengths and improve digital system performance. However, heat removal is more difficult in ...
DAC
2003
ACM
14 years 18 days ago
2003
ACM
In recent years, due to rapid advances in VLSI manufacturing technology capable of packing more and more devices and wires on a chip, crosstalk has emerged as a serious problem af...
DAC
2003
ACM
14 years 18 days ago
2003
ACM
In this paper we propose a partitioning-based placement algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization. The placement...
ISLPED
2004
ACM
14 years 23 days ago
2004
ACM
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high s...