43 search results - page 8 / 9 » Area optimization of multi-cycle operators in high-level syn... |
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
In a behavioral synthesis system, a typical approach used to guide the scheduler is to impose hard constraints on the relative timing between operations considering performance, a...
HPCA
2000
IEEE
13 years 11 months ago
2000
IEEE
Processor architectures with tens to hundreds of arithmetic units are emerging to handle media processing applications. These applications, such as image coding, image synthesis, ...
SIGMOD
2009
ACM
14 years 7 months ago
2009
ACM
SQL tuning--the attempt to improve a poorly-performing execution plan produced by the database query optimizer-is a critical aspect of database performance tuning. Ironically, as ...
DAC
2010
ACM
13 years 11 months ago
2010
ACM
As device size shrinks to the nanometer range, FPGAs are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very impo...
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
We present an architecture for a synthesizable datapathoriented Field Programmable Gate Array (FPGA) core which can be used to provide post-fabrication flexibility to a Systemon-...