67 search results - page 2 / 14 » Array-of-arrays architecture for parallel floating point mul... |
ERSA
2004
13 years 11 months ago
2004
Abstract-- Technological advances have made FPGAs an attractive platform for the acceleration of complex scientific applications. These applications demand high performance and hig...
DSD
2003
IEEE
14 years 3 months ago
2003
IEEE
Double precision floating-point arithmetic is inadequate for many scientific computations. This paper presents the design of a quadruple precision floating-point multiplier tha...
FPL
2007
Springer
14 years 4 months ago
2007
Springer
This paper presents a novel architecture for domain-specific FPGA devices. This architecture can be optimised for both speed and density by exploiting domain-specific informatio...
ARITH
1999
IEEE
14 years 2 months ago
1999
IEEE
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
FPL
2006
Springer
14 years 2 months ago
2006
Springer
FPGAs have reached densities that can implement floatingpoint applications, but floating-point operations still require a large amount of FPGA resources. One major component of IE...