403 search results - page 54 / 81 » Aurora: An Approach to High Throughput Parallel Simulation |
164
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ISCA
2003
IEEE
15 years 11 months ago
2003
IEEE
To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...
171
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FCCM
2006
IEEE
16 years 20 hour ago
2006
IEEE
It has been shown that a small number of FPGAs can significantly accelerate certain computing tasks by up to two or three orders of magnitude. However, particularly intensive lar...
113
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ICDCSW
2005
IEEE
15 years 11 months ago
2005
IEEE
— In this paper, we propose a new approach called MAFIC (MAlicious Flow Identification and Cutoff) to support adaptive packet dropping to fend off DDoS attacks. MAFIC works by j...
183
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PODC
2011
ACM
14 years 8 months ago
2011
ACM
Internet supercomputing is becoming an increasingly popular means for harnessing the power of a vast number of interconnected computers. This comes at a cost substantially lower t...
191
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MAM
2002
15 years 5 months ago
2002
Bus-based shared memory multiprocessors with private caches and snooping write-invalidate cache coherence protocols are dominant form of small- to medium-scale parallel machines t...