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DAC
1999
ACM
15 years 7 months ago
Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...
Joon-Seo Yim, Chong-Min Kyung
108
Voted
CODES
2007
IEEE
15 years 9 months ago
Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions
High-end biomedical applications are a good target for specificpurpose system-on-chip (SoC) implementations. Human heart electrocardiogram (ECG) real-time monitoring and analysis ...
Iyad Al Khatib, Davide Bertozzi, Axel Jantsch, Luc...
111
Voted
WORDS
2003
IEEE
15 years 8 months ago
A Framework for Scalable Analysis and Design of System-wide Graceful Degradation in Distributed Embedded Systems
We present a framework that will enable scalable analysis and design of graceful degradation in distributed embedded systems. We define graceful degradation in terms of utility. A...
Charles P. Shelton, Philip Koopman, William Nace
104
Voted
COR
2007
133views more  COR 2007»
15 years 2 months ago
Reverse logistics network design with stochastic lead times
This work is concerned with the efficient design of a reverse logistics network using an extended version of models currently found in the literature. Those traditional, basic mo...
Kris Lieckens, Nico Vandaele
TC
2008
15 years 2 months ago
Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model
Abstract-- Preventing silicon chips from negative, even disastrous thermal hazards has become increasingly challenging these days; considering thermal effects early in the design c...
Wei Huang, Karthik Sankaranarayanan, Kevin Skadron...