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DAC
2003
ACM
14 years 10 months ago
Multilevel floorplanning/placement for large-scale modules using B*-trees
We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-sca...
Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hanna...
DAC
2009
ACM
14 years 10 months ago
Analysis and mitigation of process variation impacts on Power-Attack Tolerance
Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impac...
Lang Lin, Wayne P. Burleson
DAC
2002
ACM
14 years 10 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
DAC
2002
ACM
14 years 10 months ago
Combined BEM/FEM substrate resistance modeling
For present-day micro-electronic designs, it is becoming ever more important to accurately model substrate coupling effects. Basically, either a Finite Element Method (FEM) or a B...
Eelco Schrik, N. P. van der Meijs
DAC
2004
ACM
14 years 10 months ago
Efficient on-line testing of FPGAs with provable diagnosabilities
We present novel and efficient methods for on-line testing in FPGAs. The testing approach uses a ROving TEster (ROTE), which has provable diagnosabilities and is also faster than ...
Vinay Verma, Shantanu Dutt, Vishal Suthar