Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
In this paper we present a new efficient algorithm for retiming sequential circuits with edge-triggered registers under both setup and hold constraints. Compared with the previous...
Design and validation of mixed-signal integrated systems require evel model abstractions. Generalized Volterra series based models have been successfully applied for analog and RF...
The negative effect of electromigration on signal and power line lifetime and functional reliability is an increasingly important problem for the physical design of integrated cir...
This paper presents a unifying framework for the modeling of asynchronous pipeline circuits. A pipeline protocol is captured in a graph-based model which defines the partial order...