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Publication
576views
15 years 9 months ago
Within-die Process Variations: How Accurately can They Be Statistically Modeled?
Within-die process variations arise during integrated circuit (IC) fabrication in the sub-100nm regime. These variations are of paramount concern as they deviate the performance of...
Brendan Hargreaves, Henrik Hult, Sherief Reda
DAC
2006
ACM
14 years 10 months ago
Gain-based technology mapping for minimum runtime leakage under input vector uncertainty
The gain-based technology mapping paradigm has been successfully employed for finding minimum delay and minimum area mappings. However, existing gain-based technology mappers fail...
Ashish Kumar Singh, Murari Mani, Ruchir Puri, Mich...
DAC
2006
ACM
14 years 10 months ago
FLAW: FPGA lifetime awareness
Aggressive scaling of technology has an adverse impact on the reliability of VLSI circuits. Apart from increasing transient error susceptibility, the circuits also become more vul...
Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie,...
DAC
1998
ACM
14 years 10 months ago
Maximum Power Estimation Using the Limiting Distributions of Extreme Order Statistics
In this paper we present a statistical method for estimating the maximum power consumption in VLSI circuits. The method is based on the theory of extreme order statistics applied ...
Qinru Qiu, Qing Wu, Massoud Pedram
GECCO
2008
Springer
201views Optimization» more  GECCO 2008»
13 years 11 months ago
Advanced techniques for the creation and propagation of modules in cartesian genetic programming
The choice of an appropriate hardware representation model is key to successful evolution of digital circuits. One of the most popular models is cartesian genetic programming, whi...
Paul Kaufmann, Marco Platzner