510 search results - page 85 / 102 » Automated Design of Quantum Circuits |
DAC
2008
ACM
14 years 11 months ago
2008
ACM
Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. T...
DAC
2003
ACM
14 years 10 months ago
2003
ACM
We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program ...
DAC
2005
ACM
14 years 10 months ago
2005
ACM
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
TCAD
2010
13 years 4 months ago
2010
Design debugging is a major bottleneck in modern VLSI design flows as both the design size and the length of the error trace contribute to its inherent complexity. With typical des...
DAC
2009
ACM
14 years 11 months ago
2009
ACM
In this paper, we propose an effective algorithm flow to handle largescale mixed-size placement. The basic idea is to use floorplanning to guide the placement of objects at the gl...