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CODES
2005
IEEE
14 years 3 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
DATE
2007
IEEE
112views Hardware» more  DATE 2007»
14 years 4 months ago
Automatic synthesis of compressor trees: reevaluating large counters
Despite the progress of the last decades in electronic design automation, arithmetic circuits have always received way less attention than other classes of digital circuits. Logic...
Ajay K. Verma, Paolo Ienne
CHES
2005
Springer
82views Cryptology» more  CHES 2005»
14 years 3 months ago
Masking at Gate Level in the Presence of Glitches
Abstract. It has recently been shown that logic circuits in the implementation of cryptographic algorithms, although protected by “secure” random masking schemes, leak side-cha...
Wieland Fischer, Berndt M. Gammel
FPGA
2006
ACM
224views FPGA» more  FPGA 2006»
14 years 1 months ago
Flexible implementation of genetic algorithms on FPGAs
In this paper, we propose a technique to flexibly implement genetic algorithms for various problems on FPGAs. For the purpose, we propose a basic architecture for GA which consist...
Tatsuhiro Tachibana, Yoshihiro Murata, Naoki Shiba...
DAC
2005
ACM
14 years 10 months ago
Temperature-aware resource allocation and binding in high-level synthesis
Physical phenomena such as temperature have an increasingly important role in performance and reliability of modern process technologies. This trend will only strengthen with futu...
Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...