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» Automated Logical Verification Based on Trace Abstractions
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DAC
2003
ACM
14 years 8 months ago
Support vector machines for analog circuit performance representation
The use of Support Vector Machines (SVMs) to represent the performance space of analog circuits is explored. In abstract terms, an analog circuit maps a set of input design parame...
Fernando De Bernardinis, Michael I. Jordan, Albert...
ICST
2009
IEEE
13 years 5 months ago
Putting Formal Specifications under the Magnifying Glass: Model-based Testing for Validation
A software development process is conceptually an abstract form of model transformation, starting from an enduser model of requirements, through to a system model for which code c...
Emine G. Aydal, Richard F. Paige, Mark Utting, Jim...
IFIP12
2009
13 years 5 months ago
An Expert System Based on Parametric Net to Support Motor Pump Multi-Failure Diagnostic
Abstract Early failure detection in motor pumps is an important issue in prediction maintenance. An efficient condition-monitoring scheme is capable of providing warning and predic...
Flavia Cristina Bernardini, Ana Cristina Bicharra ...
KR
1992
Springer
13 years 11 months ago
Embedding Defaults into Terminological Knowledge Representation Formalisms
Abstract, We consider the problem of integrating Reiter's default logic into terminological representation systems. It turns out that such an integration is less straightforwa...
Franz Baader, Bernhard Hollunder
TVLSI
2010
13 years 2 months ago
Variation-Aware System-Level Power Analysis
Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufact...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...