This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimizatio...
We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, ...
In this paper we propose a novel parameterized macromodeling technique for analog circuits. Unlike traditional macromodels that are only extracted for a small variation space, our...
We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simul...
The requirement for power system operators to respond more efficiently to the stressed power system conditions that may create large number of alarms asks fort advanced alarm proc...