This paper presents experimental results for a parallel pipeline STAP system with I/O task implementation using the parallel file systems on the Intel Paragon and the IBM SP. In ...
Wei-keng Liao, Alok N. Choudhary, Donald Weiner, P...
- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...
Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong,...
Data, addresses, and instructions are compressed by maintaining only significant bytes with two or three extension bits appended to indicate the significant byte positions. This s...
Abstract. Pipeline morphing is a simple but e ective technique for recon guring pipelined FPGA designs at run time. By overlapping computation and recon guration, the latency assoc...
Wayne Luk, Nabeel Shirazi, Shaori Guo, Peter Y. K....
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip...
Jongman Kim, Dongkook Park, Theo Theocharides, Nar...