4359 search results - page 15 / 872 » Automated Pipeline Design |
ICCAD
1993
IEEE
1993
IEEE
Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors
14 years 2 days ago
— One major problem in pipeline synthesis is the detection and resolution of pipeline hazards. In this paper we present a new solution to the problem in the domain of pipelined a...
FPL
2003
Springer
14 years 1 months ago
2003
Springer
We discuss high-performance programmable asynchronous pipeline arrays (PAPAs). These pipeline arrays are coarse-grain field programmable gate arrays (FPGAs) that realize high data...
DAC
2009
ACM
14 years 9 months ago
2009
ACM
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
TVLSI
2008
13 years 7 months ago
2008
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
In designing bus based systems with parallel and pipelined architecture, it is important to derive a real time budget (a specified execution time limit) for each task of a bus bas...