Sciweavers

4359 search results - page 165 / 872
» Automated Pipeline Design
Sort
View
104
Voted
ISQED
2009
IEEE
115views Hardware» more  ISQED 2009»
15 years 10 months ago
TuneLogic: Post-silicon tuning of dual-Vdd designs
Modern CMOS manufacturing processes have significant variability, which necessitates guard banding to achieve reasonable yield. It is our thesis that variability should be addres...
Stephen Bijansky, Sae Kyu Lee, Adnan Aziz
93
Voted
ASAP
2007
IEEE
101views Hardware» more  ASAP 2007»
15 years 9 months ago
Hardware Design of a Binary Integer Decimal-based IEEE P754 Rounding Unit
Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it were recently added to the draft revision of the IEEE 754 Standard (IEEE P754)....
Charles Tsen, Michael J. Schulte, Sonia Gonzalez-N...
CHES
2003
Springer
146views Cryptology» more  CHES 2003»
15 years 7 months ago
Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs
Abstract. Performance evaluation of the Advanced Encryption Standard candidates has led to intensive study of both hardware and software implementations. However, although plentifu...
François-Xavier Standaert, Gaël Rouvro...
LCTRTS
2001
Springer
15 years 8 months ago
Power-Aware Design Synthesis Techniques for Distributed Real-Time Systems
This paper presents an end-to-end synthesis technique for lowpower distributed real-time system design. This technique synthesizes supply voltages of resources to optimize system-...
Dong-In Kang, Stephen P. Crago, Jinwoo Suh
132
Voted
HPCA
2000
IEEE
15 years 7 months ago
Design of a Parallel Vector Access Unit for SDRAM Memory Systems
We are attacking the memory bottleneck by building a “smart” memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting appl...
Binu K. Mathew, Sally A. McKee, John B. Carter, Al...