This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the conf...
In this paper, we present two novel synchronization approaches to support data flow in clockless designs using single-rail encoding. Both approaches are based on self-resetting st...
Development environments based on ActiveX controls and JavaBeans are marketed as "visual programming" platforms; in practice their visual dimension is limited to the des...
In this paper, we propose a technique to flexibly implement genetic algorithms for various problems on FPGAs. For the purpose, we propose a basic architecture for GA which consist...