4359 search results - page 47 / 872 » Automated Pipeline Design |
ICCAD
2008
IEEE
14 years 5 months ago
2008
IEEE
— This paper presents a method for correct-by-construction microarchitectural pipelining that handles cyclic systems with dependencies between iterations. Our method combines pre...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
Functional validation is a major bottleneck in pipelined processor design. Simulation using functional test vectors is the most widely used form of processor validation. While exi...
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
DAC
2005
ACM
13 years 10 months ago
2005
ACM
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
INFOCOM
2003
IEEE
14 years 1 months ago
2003
IEEE
— Pipelined ASIC architectures are increasingly being used in forwarding engines for high speed IP routers. We explore optimization issues in the design of memory-efficient data...