106 search results - page 16 / 22 » Automated Source-Level Error Localization in Hardware Design... |
DAC
2005
ACM
14 years 8 months ago
2005
ACM
While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the l...
ICCAD
1999
IEEE
13 years 11 months ago
1999
IEEE
Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous spee...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
For a space compactor, degradation of fault detection capability caused by the masking effects from unknown values is much more serious than that caused by error masking (i.e. ali...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
In this paper, a Triangularization Based Structure preserving (TBS) model order reduction is proposed to verify power integrity of on-chip structured power grid. The power grid is...
ISPD
2009
ACM
14 years 2 months ago
2009
ACM
Gate sizing and threshold voltage (Vt) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivity-driven h...