Sciweavers

106 search results - page 8 / 22
» Automated Source-Level Error Localization in Hardware Design...
Sort
View
MSE
2005
IEEE
150views Hardware» more  MSE 2005»
14 years 1 months ago
A Cohesive FPGA-Based System-on-Chip Design Curriculum
A graduate-level computer engineering course sequence at the OGI School of Science and Engineering teaches state-of-the-art digital system design practices and system-on-chip desi...
John D. Lynch, Daniel Hammerstrom, Roy Kravitz
DAC
2006
ACM
14 years 8 months ago
Shielding against design flaws with field repairable control logic
Correctness is a paramount attribute of any microprocessor design; however, without novel technologies to tame the increasing complexity of design verification, the amount of bugs...
Ilya Wagner, Valeria Bertacco, Todd M. Austin
DAC
2004
ACM
14 years 8 months ago
Synthesizing interconnect-efficient low density parity check codes
Error correcting codes are widely used in communication and storage applications. Codec complexity has usually been measured with a software implementation in mind. A recent hardw...
Marghoob Mohiyuddin, Amit Prakash, Adnan Aziz, Way...
DAC
2004
ACM
14 years 8 months ago
Automated energy/performance macromodeling of embedded software
Efficient energy and performance estimation of embedded software is a critical part of any system-level design flow. Macromodeling based estimation is an attempt to speed up estim...
Anish Muttreja, Anand Raghunathan, Srivaths Ravi, ...
ISSS
2002
IEEE
142views Hardware» more  ISSS 2002»
14 years 12 days ago
Energy/Power Estimation of Regular Processor Arrays
We propose a high-level analytical model for estimating the energy and/or power dissipation in VLSI processor (systolic) array implementations of loop programs, particularly for i...
Sanjay V. Rajopadhye, Steven Derrien