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» Automatic Clock Abstraction from Sequential Circuits
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ASPDAC
2005
ACM
78views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Timing driven track routing considering coupling capacitance
Abstract— As VLSI technology enters the ultra-deep submicron era, wire coupling capacitance starts to dominate self capacitance and can no longer be neglected in timing driven ro...
Di Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra
ASPDAC
2006
ACM
124views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Functional modeling techniques for efficient SW code generation of video codec applications
–Architectures with multiple programmable cores are becoming more attractive for video codec applications because they can provide highly concurrent computation and support multi...
Sang-Il Han, Soo-Ik Chae, Ahmed Amine Jerraya
ICCAD
2000
IEEE
119views Hardware» more  ICCAD 2000»
14 years 1 days ago
Synthesis of Operation-Centric Hardware Descriptions
Most hardware description frameworks, whether schematic or textual, use cooperating finite state machines (CFSM) as the underlying abstraction. In the CFSM framework, a designer ...
James C. Hoe, Arvind
RSP
2003
IEEE
176views Control Systems» more  RSP 2003»
14 years 27 days ago
Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment
This paper describes the early analysis and estimation features currently implemented in the Berkeley Emulation Engine (BEE) system. BEE is an integrated rapid prototyping and des...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, A...
FPL
2001
Springer
96views Hardware» more  FPL 2001»
14 years 4 days ago
System Level Tools for DSP in FPGAs
Abstract. Visual data ow environments are ideally suited for modeling digital signal processing (DSP) systems, as many DSP algorithms are most naturally speci ed by signal ow gra...
James Hwang, Brent Milne, Nabeel Shirazi, Jeffrey ...