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DATE
2008
IEEE
115views Hardware» more  DATE 2008»
14 years 2 months ago
Synthesizing Synchronous Elastic Flow Networks
This paper describes an implementation language and synthesis system for automatically generating latency insensitive synchronous digital designs. These designs decouple behaviora...
Greg Hoover, Forrest Brewer
FPL
1999
Springer
74views Hardware» more  FPL 1999»
13 years 12 months ago
On Tool Integration in High-Performance FPGA Design Flows
Abstract. High-performance design flows for FPGAs often rely on module generators to counter coarse logic-block granularity and limited routing resources, However, the very flexi...
Andreas Koch
CODES
2000
IEEE
13 years 12 months ago
Automatic test bench generation for simulation-based validation
In current design practice synthesis tools play a key role, letting designers to concentrate on the specificationof the system being designed by carrying out repetitive tasks such...
Marcello Lajolo, Luciano Lavagno, Maurizio Rebaude...
DATE
2003
IEEE
112views Hardware» more  DATE 2003»
14 years 26 days ago
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula
System design methodology is poised to become the next big enabler for highly sophisticated electronic products. Design verification continues to be a major challenge and simulat...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...
ICCAD
1999
IEEE
84views Hardware» more  ICCAD 1999»
13 years 12 months ago
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...
Jordi Cortadella, Michael Kishinevsky, Steven M. B...