This paper develops an improved approach for hierarchical functional test generation for complex chips. In order to deal with the increasing complexity of functional test generati...
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
This paper presents a method for the automatic generation of a table-of-contents. This type of summary could serve as an effective navigation tool for accessing information in lon...
S. R. K. Branavan, Pawan Deshpande, Regina Barzila...
Recently, a deterministic algorithm based on the O-tree representation has been proposed. This method generates excellent layout results on MCNC test cases with O(n3 ) complexity,...
As microprocessors continue to evolve, many optimizations reach a point of diminishing returns. We introduce HLS, a hybrid processor simulator which uses statistical models and sy...