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DATE
2002
IEEE
94views Hardware» more  DATE 2002»
15 years 8 months ago
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis
This paper develops an improved approach for hierarchical functional test generation for complex chips. In order to deal with the increasing complexity of functional test generati...
Vivekananda M. Vedula, Jacob A. Abraham
ICCAD
2002
IEEE
142views Hardware» more  ICCAD 2002»
16 years 22 days ago
SAT and ATPG: Boolean engines for formal hardware verification
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
Armin Biere, Wolfgang Kunz
ACL
2007
15 years 5 months ago
Generating a Table-of-Contents
This paper presents a method for the automatic generation of a table-of-contents. This type of summary could serve as an effective navigation tool for accessing information in lon...
S. R. K. Branavan, Pawan Deshpande, Regina Barzila...
ISPD
2000
ACM
92views Hardware» more  ISPD 2000»
15 years 8 months ago
An enhanced perturbing algorithm for floorplan design using the O-tree representation
Recently, a deterministic algorithm based on the O-tree representation has been proposed. This method generates excellent layout results on MCNC test cases with O(n3 ) complexity,...
Yingxin Pang, Chung-Kuan Cheng, Takeshi Yoshimura
ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
15 years 8 months ago
HLS: combining statistical and symbolic simulation to guide microprocessor designs
As microprocessors continue to evolve, many optimizations reach a point of diminishing returns. We introduce HLS, a hybrid processor simulator which uses statistical models and sy...
Mark Oskin, Frederic T. Chong, Matthew K. Farrens