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130
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ASPDAC
2001
ACM
15 years 7 months ago
2001
ACM
This paper describes a novel approach to high-level synthesis of complex pipelined circuits, including pipelined circuits with feedback. This approach combines a high-level, modula...
135
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GLVLSI
2002
IEEE
15 years 9 months ago
2002
IEEE
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
148
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BIRTHDAY
2007
Springer
15 years 8 months ago
2007
Springer
We present a verification methodology for cooperating traffic agents covering analysis of cooperation strategies, realization of strategies through control, and implementation of c...
137
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DATE
2009
IEEE
15 years 11 months ago
2009
IEEE
In the field of chip design, hardware module reuse is a standard solution to the increasing complexity of chip architecture and the pressures to reduce time to market. In the abs...
138
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DATE
2005
IEEE
15 years 9 months ago
2005
IEEE
Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design process. A significant bottleneck in the validatio...