188 search results - page 7 / 38 » Automatic Model Refinement for Fast Architecture Exploration |
ASPDAC
2009
ACM
14 years 5 days ago
2009
ACM
— This paper proposes the first automatic approach to simultaneously generate Cycle Accurate and Cycle Count Accurate transaction level bus models. Since TLM (Transaction Level M...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
In this paper, we present an approach for automatic synthesis of System on Chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is ...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
The creation of an FPGA requires extensive transistor-level design. This is necessary for both the final design, and during architecture exploration, when many different logic and...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constr...
ENTCS
2010
13 years 4 months ago
2010
Model-driven performance prediction methods require detailed design models to evaluate the performance of software systems during early development stages. However, the complexity...