57 search results - page 6 / 12 » Automatic On-chip Memory Minimization for Data Reuse |
ISCA
2010
IEEE
14 years 15 days ago
2010
IEEE
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
PLDI
2012
ACM
11 years 10 months ago
2012
ACM
Automatic parallelization is a promising strategy to improve application performance in the multicore era. However, common programming practices such as the reuse of data structur...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...
CODES
2001
IEEE
13 years 11 months ago
2001
IEEE
Compiler technology is becoming a key component in the design of embedded systems, mostly due to increasing participation of software in the design process. Meeting system-level ob...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
1 The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requireme...