The focus of this paper is on reducing the complexity in verification by exploiting modularity at various levels: in specification, in verification, and structurally. For specifica...
Johannes Faber, Carsten Ihlemann, Swen Jacobs, Vio...
In this paper we present an algorithm for automatic extraction of system behavior from a structural Verilog specification. The algorithm generates a series-parallel poset expressi...
This paper gives an overview of results of the project "Beyond Timed Automata" carried out in the Collaborative Research Center AVACS (Automatic Verification and Analysi...
Dynamic communication systems (DCS) are complex because of their unboundedness in several dimensions. They have an unbounded and changing number of objects, a dynamically changing...
A central problem in functional verification is to check that a circuit block is producing correct outputs while enforcing that the environment is providing legal inputs. To attac...