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» Automatic Verification of Timed Circuits
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ICCD
2005
IEEE
169views Hardware» more  ICCD 2005»
14 years 7 months ago
ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology
— Since rapid progress has been made in device improvement and integration of small carbon nanotube fieldeffect transistors (CNFETs) circuits, the time has come for developing c...
Wei Zhang, Niraj K. Jha
ICCAD
2003
IEEE
205views Hardware» more  ICCAD 2003»
14 years 4 months ago
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
Aseem Agarwal, David Blaauw, Vladimir Zolotov
ATVA
2009
Springer
142views Hardware» more  ATVA 2009»
14 years 2 months ago
TAPAAL: Editor, Simulator and Verifier of Timed-Arc Petri Nets
TAPAAL is a new platform independent tool for modelling, simulation and verification of timed-arc Petri nets. TAPAAL provides a stand-alone editor and simulator, while the verifica...
Joakim Byg, Kenneth Yrke Jørgensen, Jir&iac...
ICASSP
2009
IEEE
14 years 5 months ago
Automatic pronunciation verification of english letter-names for early literacy assessment of preliterate children
Children need to master reading letter-names and lettersounds before reading phrases and sentences. Pronunciation assessment of letter-names and letter-sounds read aloud is an imp...
Matthew Black, Joseph Tepperman, Abe Kazemzadeh, S...
DAC
2006
ACM
14 years 12 months ago
Criticality computation in parameterized statistical timing
Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult ...
Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswa...