302 search results - page 20 / 61 » Automatic Verification of Timed Circuits |
TCAD
2002
13 years 10 months ago
2002
As very large scale integration (VLSI) circuit speed rapidly increases, the inductive effects of interconnect lines strongly impact the signal integrity of a circuit. Since these i...
DAC
2003
ACM
14 years 12 months ago
2003
ACM
In the way they cope with variability, present-day methodologies are onerous, pessimistic and risky, all at the same time! Dealing with variability is an increasingly important as...
DAC
1997
ACM
14 years 3 months ago
1997
ACM
Cr, As the complexity of high-performance microprocessor increases, functional verification becomes more and more difficult and RTL simulation emerges as the bottleneck of the des...
EPK
2006
14 years 9 days ago
2006
Abstract: Event-driven Process Chains (EPCs) are a commonly used modelling technique for design and documentation of business processes. Although EPCs have an easy-to-understand no...
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
A methodology is proposed to efficiently estimate the substrate noise generated by large scale aggressor circuits. Small spatial voltage differences within the ground distribution...