302 search results - page 25 / 61 » Automatic Verification of Timed Circuits |
DAC
2008
ACM
14 years 12 months ago
2008
ACM
Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. T...
GLVLSI
2008
IEEE
14 years 5 months ago
2008
IEEE
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...
CAV
2001
Springer
14 years 2 months ago
2001
Springer
We consider the randomized consensus protocol of Aspnes and Herlihy for achieving agreement among N asynchronous processes that communicate via read/write shared registers. The alg...
ICCAD
1998
IEEE
14 years 3 months ago
1998
IEEE
Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is partic...
FPL
1999
Springer
14 years 3 months ago
1999
Springer
Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional ...