302 search results - page 2 / 61 » Automatic Verification of Timed Circuits |
DAC
2007
ACM
14 years 9 months ago
2007
ACM
Abstract-- The PPV is a robust phase domain macromodel for oscillators. It has been proven to predict oscillators' responses correctly under small signal perturbations, and ca...
ICCAD
2002
IEEE
14 years 5 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper presents an innovative approach for analogue and mixed-signal verification. It consists in a “verification kit” that makes use of concepts used in state-of-art digi...
DATE
2002
IEEE
14 years 1 months ago
2002
IEEE
ions + Assume Guarantee + Induction GOAL: Formal verification of the IPCMOS architecture
ICCAD
2003
IEEE
14 years 5 months ago
2003
IEEE
This paper presents an efficient method for verifying hazard freedom in timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that utilize explicit tim...