302 search results - page 33 / 61 » Automatic Verification of Timed Circuits |
GECCO
2008
Springer
14 years 16 hour ago
2008
Springer
In this work an improvement of an initial approach to design Artificial Neural Networks to forecast Time Series is tackled, and the automatic process to design Artificial Neural N...
DDECS
2007
IEEE
14 years 5 months ago
2007
IEEE
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...
MJ
2007
13 years 10 months ago
2007
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...
FCCM
2005
IEEE
14 years 4 months ago
2005
IEEE
When designing systems-on-a-chip (SoCs), a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be ...
TCAD
1998
13 years 10 months ago
1998
Abstract—This paper presents an aggressive optimization technique targeting combinational logic circuits. Starting from an initial implementation mapped on a given technology lib...