302 search results - page 6 / 61 » Automatic Verification of Timed Circuits |
ASYNC
1999
IEEE
14 years 2 months ago
1999
IEEE
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austi...
JIRS
2007
13 years 9 months ago
2007
A detailed step-by-step approach is presented to optimize, standardize, and automate the process of unmanned vehicle controller design, evaluation, validation and verification, fol...
DAC
2003
ACM
14 years 10 months ago
2003
ACM
With the scaling of technology, power grid noise is becoming increasingly significant for circuit performance. A typical power grid circuit contains millions of linear elements, m...
ECBS
2007
IEEE
14 years 1 months ago
2007
IEEE
We present in this paper a new approach for the automatic verification and performance analysis of SysML activity diagrams. Since timeliness is important in the design and analysi...
ICCAD
1999
IEEE
14 years 2 months ago
1999
IEEE
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...