961 search results - page 14 / 193 » Automatic design synthesis with artificial intelligence tech... |
ICCAD
2002
IEEE
14 years 3 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
FLAIRS
2003
13 years 8 months ago
2003
This paper presents a semantic labeling technique based on information encoded in FrameNet. Sentences labeled for frames relevant to any new Information Extraction domain enable t...
DAC
2008
ACM
14 years 7 months ago
2008
ACM
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
IWANN
2009
Springer
14 years 1 months ago
2009
Springer
This paper proposes a new evolutionary method for generating ANNs. In this method, a simple real-number string is used to codify both architecture and weights of the networks. Ther...
ISLPED
2003
ACM
13 years 12 months ago
2003
ACM
This paper proposes two very fast graph theoretic heuristics for the low power binding problem given fixed number of resources and multiple architectures for the resources. First...