27 search results - page 4 / 6 » Automatic memory partitioning and scheduling for throughput ... |
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
ISCA
2010
IEEE
14 years 19 days ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
CORR
2010
Springer
13 years 4 months ago
2010
Springer
Energy consumption is a critical design issue in real-time systems, especially in battery- operated systems. Maintaining high performance, while extending the battery life between...
ASPLOS
2008
ACM
13 years 9 months ago
2008
ACM
The recent shift in the industry towards chip multiprocessor (CMP) designs has brought the need for multi-threaded applications to mainstream computing. As observed in several lim...
ISCA
2002
IEEE
14 years 14 days ago
2002
IEEE
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...