47 search results - page 2 / 10 » Automatic memory reductions for RTL model verification |
RSP
2003
IEEE
14 years 4 months ago
2003
IEEE
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
DAC
2005
ACM
14 years 11 months ago
2005
ACM
el Predicate Abstraction and Refinement for Verifying RTL Verilog Himanshu Jain CMU SCS, Pittsburgh, PA 15213 Daniel Kroening ETH Z?urich, Switzerland Natasha Sharygina CMU SCS an...
TCAD
2008
13 years 10 months ago
2008
el Predicate Abstraction and Refinement Techniques for Verifying RTL Verilog Himanshu Jain, Daniel Kroening, Natasha Sharygina, and Edmund M. Clarke, Fellow, IEEE As a first step, ...
DAC
1996
ACM
14 years 3 months ago
1996
ACM
We reduce the state explosion problem in automatic verification of finite-state systems by automatically collapsing subgraphs of the aph into abstract states. The key idea of the ...
VLSID
2004
IEEE
14 years 11 months ago
2004
IEEE
Recent advances on language based software toolkit generation enables performance driven exploration of embedded systems by exploiting the application behavior. There is a need fo...