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DAC
2006
ACM
14 years 7 months ago
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
Yu Hu, Yan Lin, Lei He, Tim Tuan
POPL
2009
ACM
14 years 7 months ago
SPEED: precise and efficient static estimation of program computational complexity
This paper describes an inter-procedural technique for computing symbolic bounds on the number of statements a procedure executes in terms of its scalar inputs and user-defined qu...
Sumit Gulwani, Krishna K. Mehra, Trishul M. Chilim...
ICCAD
2003
IEEE
144views Hardware» more  ICCAD 2003»
14 years 3 months ago
A High-level Interconnect Power Model for Design Space Exploration
— In this paper, we present a high-level power model to estimate the power consumption in semi-global and global interconnects. Such interconnects are used for communications bet...
Pallav Gupta, Lin Zhong, Niraj K. Jha
ICIP
2000
IEEE
14 years 8 months ago
Analysis of Corneal Images for Assessing Contact Lens Trauma
Contact lens wearers are often affected by a condition known as conjuctival hyperaemia. This condition is characterised by dilated blood vessels visible in the sclera (the white p...
Janine Cullen, Paul W. Fieguth, Shane Pounder, Kim...
DAC
2008
ACM
14 years 7 months ago
Low power passive equalizer optimization using tritonic step response
A low power passive equalizer using RL terminator is proposed and optimized in this work. The equalizer includes an inductor in series with the resistive terminator, which boosts ...
Ling Zhang, Wenjian Yu, Haikun Zhu, Alina Deutsch,...