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ITC
2003
IEEE
222views Hardware» more  ITC 2003»
14 years 23 days ago
Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random Simulation
Functional verification of complex designs largely relies on the use of simulation in conjunction high-level verification languages (HVL) and test-bench automation (TBA) tools. In...
Mahesh A. Iyer
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
14 years 1 months ago
Two-level microprocessor-accelerator partitioning
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move softw...
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank V...
ICCAD
2002
IEEE
124views Hardware» more  ICCAD 2002»
14 years 4 months ago
Symbolic pointer analysis
— One of the bottlenecks in the recent movement of hardware synthesis from behavioral C programs is the difficulty in reasoning about runtime pointer values at compile time. The...
Jianwen Zhu
ICCAD
2007
IEEE
99views Hardware» more  ICCAD 2007»
14 years 4 months ago
Automating post-silicon debugging and repair
Modern IC designs have reached unparalleled levels of complexity, resulting in more and more bugs discovered after design tape-out However, so far only very few EDA tools for post...
Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
DAC
1999
ACM
13 years 11 months ago
Common-Case Computation: A High-Level Technique for Power and Performance Optimization
This paper presents a design methodology, called common-case computation (CCC), and new design automation algorithms for optimizing power consumption or performance. The proposed ...
Ganesh Lakshminarayana, Anand Raghunathan, Kamal S...