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DATE
2003
IEEE
134views Hardware» more  DATE 2003»
15 years 7 months ago
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration
The design of high performance multimedia systems in a short time force us to use IP's blocks in many designs. However, their correct integration in a design implies more com...
Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Ri...
DATE
2006
IEEE
147views Hardware» more  DATE 2006»
15 years 8 months ago
Quantitative analysis of transaction level models for the AMBA bus
The increasing complexity of embedded systems pushes system designers to higher levels of abstraction. Transaction Level Modeling (TLM) has been proposed to model ation in systems...
Gunar Schirner, Rainer Dömer
116
Voted
IPPS
1999
IEEE
15 years 6 months ago
Optimizing Irregular HPF Applications using Halos
This paper presents language features for High Performance Fortran HPF to specify non-local access patterns of distributed arrays, called halos, and to control the communication as...
Siegfried Benkner
105
Voted
DAC
2009
ACM
16 years 3 months ago
Handling don't-care conditions in high-level synthesis and application for reducing initialized registers
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
112
Voted
EMSOFT
2008
Springer
15 years 4 months ago
Energy efficient streaming applications with guaranteed throughput on MPSoCs
In this paper we present a design space exploration flow to achieve energy efficiency for streaming applications on MPSoCs while meeting the specified throughput constraints. The ...
Jun Zhu, Ingo Sander, Axel Jantsch