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» Balance Testing of Logic Circuits
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AHS
2006
IEEE
138views Hardware» more  AHS 2006»
14 years 1 months ago
Generalized Disjunction Decomposition for the Evolution of Programmable Logic Array Structures
Evolvable hardware refers to a self reconfigurable electronic circuit, where the circuit configuration is under the control of an evolutionary algorithm. Evolvable hardware has sh...
Emanuele Stomeo, Tatiana Kalganova, Cyrille Lamber...
KR
1992
Springer
13 years 11 months ago
Abductive Plan Recognition and Diagnosis: A Comprehensive Empirical Evaluation
While it has been realized for quite some time within AI that abduction is a general model of explanation for a variety of tasks, there have been no empirical investigations into ...
Hwee Tou Ng, Raymond J. Mooney
ETS
2011
IEEE
230views Hardware» more  ETS 2011»
12 years 7 months ago
Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis
—As circuits continue to scale to smaller feature sizes, wearout and latent defects are expected to cause an increasing number of errors in the field. Online error detection tec...
Nuno Alves, Y. Shi, N. Imbriglia, Jennifer Dworak,...
ITC
2003
IEEE
158views Hardware» more  ITC 2003»
14 years 23 days ago
Extraction Error Diagnosis and Correction in High-Performance Designs
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires ...
Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikara...
ASPDAC
2007
ACM
80views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic
Abstract-- A complementary ferroelectriccapacitor (CFC) logic-circuit style is proposed for a compact and standby-power-free content-addressable memory (CAM). Since the use of the ...
Shoun Matsunaga, Takahiro Hanyu, Hiromitsu Kimura,...