233 search results - page 31 / 47 » Balance Testing of Logic Circuits |
IOLTS
2008
IEEE
14 years 2 months ago
2008
IEEE
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient err...
TODAES
2002
13 years 7 months ago
2002
ct Cross-coupled noise analysis has become a critical concern in today's VLSI designs. Typically, noise analysis makes an assumption that all aggressing nets can simultaneousl...
ET
2002
13 years 7 months ago
2002
In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our te...
ATS
2003
IEEE
14 years 26 days ago
2003
IEEE
Capacitive crosstalk can give rise to slowdown of signals that can propagate to a circuit output and create a functional error. A test generation methodology, called XGEN, was dev...
DATE
2000
IEEE
13 years 12 months ago
2000
IEEE
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...