13 search results - page 1 / 3 » Balancing System Level Pipelines with Stage Voltage Scaling |
ISVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper presents an approach to dynamically balance the pipeline by scaling the stage supply voltages. Simulation results show that by such an approach about 50% improvement in...
ISLPED
2004
ACM
14 years 1 months ago
2004
ACM
The quadratic relationship between voltage and energy has made dynamic voltage scaling (DVS) one of the most powerful techniques to reduce system power demands. Recently, techniqu...
MICRO
2003
IEEE
14 years 26 days ago
2003
IEEE
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
MICRO
2008
IEEE
14 years 2 months ago
2008
IEEE
Scaling of CMOS feature size has long been a source of dramatic performance gains. However, the reduction in voltage levels has not been able to match this rate of scaling, leadin...
CASES
2008
ACM
13 years 9 months ago
2008
ACM
Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip te...