271 search results - page 17 / 55 » Bandwidth-Friendly Cache Hierarchy |
CORR
2007
Springer
13 years 10 months ago
2007
Springer
Safety-criticalembeddedsystems having to meet real-time constraints are to be highlypredictable in order to guarantee at design time that certain timing deadlines will always be m...
DAC
1999
ACM
14 years 11 months ago
1999
ACM
In embedded system design, the designer has to choose an onchip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory...
ISCA
2007
IEEE
13 years 9 months ago
2007
IEEE
The center of gravity of computer architecture is moving toward memory systems. Barring breakthrough microarchitectural techniques to move processor performance to higher levels, ...
ICCAD
2002
IEEE
14 years 6 months ago
2002
IEEE
Embedded system programs tend to spend much time in small loops. Introducing a very small loop cache into the instruction memory hierarchy has thus been shown to substantially red...
MICRO
2007
IEEE
14 years 4 months ago
2007
IEEE
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...