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USENIX
1996
13 years 11 months ago
A Hierarchical Internet Object Cache
: This paper discussesthedesignandperformance of a hierarchical proxy-cache designed to make Internet information systems scale better. The design was motivated by our earlier trac...
Anawat Chankhunthod, Peter B. Danzig, Chuck Neerda...
DAC
2009
ACM
14 years 11 months ago
A DVS-based pipelined reconfigurable instruction memory
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
Zhiguo Ge, Tulika Mitra, Weng-Fai Wong
DATE
2009
IEEE
110views Hardware» more  DATE 2009»
14 years 4 months ago
Light NUCA: A proposal for bridging the inter-cache latency gap
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...
Darío Suárez Gracia, Teresa Monreal,...
EUROPAR
1999
Springer
14 years 2 months ago
Annotated Memory References: A Mechanism for Informed Cache Management
Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...
Alvin R. Lebeck, David R. Raymond, Chia-Lin Yang, ...
DATE
2004
IEEE
159views Hardware» more  DATE 2004»
14 years 1 months ago
Compositional Memory Systems for Data Intensive Applications
To alleviate the system performance unpredictability of multitasking applications running on multiprocessor platforms with shared memory hierarchies we propose a task level set ba...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...