A methodology for hierarchicalstatistical circuit characterization which does not rely upon circuit-level Monte Carlo simulation is presented. The methodology uses principalcompon...
Eric Felt, Stefano Zanella, Carlo Guardiani, Alber...
A methodology for constructing circuit-level mismatch models and performing yield optimization is presented for CMOS analog circuits. The methodology combines statistical techniqu...
This paper presents a novel approach for synthesis of analog systems from behavioral VHDL-AMS specifications. We implemented this approach in the VASE behavioral-synthesis tool. ...
In this paper we demonstrate a potential extension of formal verification methodology in order to deal with time-domain properties of analog and mixed-signal circuits whose dynamic...
When estimating the dynamic power dissipated by a circuit dierent methods ranging from numeric analog simulation to event-driven logic simulation have been proposed. However, as ...
Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Pet...