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ISPD
2010
ACM
224views Hardware» more  ISPD 2010»
14 years 1 months ago
An analytical placer for mixed-size 3D placement
Existing 3D placement techniques are mainly used for standardcell circuits, while mixed-size placement is needed to support highlevel functional units and intellectual property (I...
Jason Cong, Guojie Luo
ISCAS
1999
IEEE
95views Hardware» more  ISCAS 1999»
13 years 11 months ago
Evaluating iterative improvement heuristics for bigraph crossing minimization
The bigraph crossing problem, embedding the two node sets of a bipartite graph G = V0;V1;E along two parallel lines so that edge crossings are minimized, has application to placeme...
Matthias F. M. Stallmann, Franc Brglez, Debabrata ...
GLVLSI
2009
IEEE
142views VLSI» more  GLVLSI 2009»
14 years 1 months ago
Hardware-accelerated gradient noise for graphics
A synthetic noise function is a key component of most computer graphics rendering systems. This pseudo-random noise function is used to create a wide variety of natural looking te...
Josef B. Spjut, Andrew E. Kensler, Erik Brunvand
ICES
2000
Springer
140views Hardware» more  ICES 2000»
13 years 10 months ago
Evolving Cellular Automata for Self-Testing Hardware
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
ISPD
1997
ACM
104views Hardware» more  ISPD 1997»
13 years 11 months ago
Timing driven placement in interaction with netlist transformations
In this paper, we present a new approach that performs timing driven placement for standard cell circuits in interaction with netlist transformations. As netlist transformations a...
Guenter Stenz, Bernhard M. Riess, Bernhard Rohflei...